Examples of analyses using the Stanford CNFET SPICE Model Wong, Modeling and Analysis of Planar Gate Capacitance for 1-D FET with Multiple Cylindrical Conducting Channels, IEEE Trans. Wong, A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application - Part II: Full Device Model and Circuit Performance Benchmarking, IEEE Trans. Wong, A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application - Part I: Model of the Intrinsic Channel Region, IEEE Trans. Jie Deng, Albert Lin, Gordon Wan Related Publications ContactĬhi-Shuen Lee - chishuen stanford edu Contributors Downloadsĭownload the HSPICE version of the CNFET model.ĭownload the Verilog A version of the CNFET model. Note: HSPICE v2.2.1 is the recommended Model Package. It is an accurate and handy tool for design exploration and verification of CNT circuits. The CNFET model can be instantiated directly in SPICE netlists to explore the impacts of CNFETs on the circuit performance. In addition, by including a full transcapacitance network, it also produces better predictions of the dynamic performance and transient response. The model has been used to perform circuit-performance comparison with the standard digital library cells between CMOS random logic and CNFET random logic. It accounts for several practical non-idealities, including the scattering of carriers due to the acoustic and optical phonons in the nanotubes, the parasitic capacitance between the gate and the source/drain formed by multiple 1D nanotubes, the gate-to-gate and gate-to-contact-plug capacitances, the charge screening among the adjacent nanotubes, the access resistance of the source/drain extension regions, the Schottky-barrier resistance at the metal-nanotube contact interfaces, and the band-to-band leakage current. The model is based on a quasi-ballistic transport picture and includes an accurate description of the capacitor network in a CNFET.

Each device may have one or more carbon nanotubes with user-specified chirality, and the effects of channel length scaling can be accurately modeled down to 20nm. The Stanford University CNFET Model is a SPICE-compatible compact model which describes enhancement-mode, unipolar MOSFETs with semiconducting single-walled carbon nanotubes as channels.

Note: A newer version of CNFET compact model, VS-CNFET model, includes data-calibrated metal-to-CNT contact resistance and direct source-to-drain tunneling current, suitable for the study of ultra-scaled CNFETs (e.g.

Download field effect transistor